1. Field of the Invention
This invention relates generally to circuits and methods for communication of digital data. More particularly this invention relates to circuits and methods for demultiplexing two channels of digital audio signals from a multiplexed serial digital data stream transferred on a serial data interface.
2. Description of Related Art
Reducing the number of pins required by an integrated circuit is an important aspect for reducing the size and cost of the integrated circuit. This is also true for monaural audio integrated circuit devices with a serial pulse code modulated (PCM) audio interface. These serial audio interfaces often have multiple channels multiplexed to a serial data stream. In a stereo audio environment, two audio signals (“left” and “right”) are digitized and then time-multiplexed for transmission over the same interface. The audio integrated circuit device has at least one additional pin that is used to select the audio integrated circuit device as either a “left” channel device or a “right” channel device. The number of input/output pins on integrated circuits that have a relatively low number of pins, impacts the size of the integrated circuit and the package into which the integrated circuit is mounted. Having fewer pins can improve the size and cost of the audio integrated circuit.
An example of a serial audio interface is the I2S developed in 1986 and revised in 1996 by Philips Semiconductor N.V. (NXP Semiconductor N.V., Eindhoven, the Netherlands) and is well known in the art. The I2S bus is designed for the transfer of only audio data, while the other signals, such as sub-coding and control, are transferred separately. To minimize the number of pins required and to keep wiring simple, a 3-line serial bus is used. Referring to FIG. 1, the I2S bus consists of a serial data SD line that has two time-multiplexed data channels (LEFT CHANNEL and RIGHT CHANNEL), a word select WS line for designating the channel boundaries, and a clock line SCK for synchronizing the transmission and reception of the data. The two time-multiplexed data channels (LEFT CHANNEL and RIGHT CHANNEL) are transmitted sequentially.
Since the transmitter and receiver have the same clock signal SCK for data transmission, the transmitter, as the master, has to generate the bit clock SCK, word-select signal WS and the serial data SD. In complex systems however, there may be several transmitters and receivers, which makes it difficult to define the master. In such systems, there is usually a system master controlling digital audio data-flow between the various ICs. Transmitters then, have to generate the serial data SD under the control of an external clock SCK and an external word-select signal WS. The transmitters then act as a slave.
The serial data is transmitted in two's complement pulse coded modulation (PCM) with the most significant bit (MSB) first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It isn't necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to ‘0’) for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word one clock period after the word select signal WS changes. Serial data SD sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal SCK. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal.
The word select line WS indicates the channel being transmitted, where the word select line WS=0 the LEFT CHANNEL is selected and where the word select line=1 the RIGHT CHANNEL is selected. The word select line WS may change either on a trailing or leading edge of the serial block (a string of bits from the most significant bit (MSB) to the least significant bit (LSB), but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The word select line WS changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous data word (n−1, n, n+1) and clear the input for the next word (n−1, n, n+1).
When this interface is used to communicate with a mono audio device (i.e. a microphone or speaker), that device must know which of the two data channels (LEFT CHANNEL and RIGHT CHANNEL) needs to be used. For small audio devices without a separate control interface, this channel selection usually requires an extra pin on the integrated circuit receiving or transmitting the serial data SD.
FIG. 2 is a block diagram of an example of a stereo microphone system using an I2S output device. The left microphone 10 and the right microphone 15 are the ADMP441 microphone from Analog Device, Norwood, Mass. The ADMP441 is a low power, digital output, omni-directional MEMS microphone with a bottom port. The complete ADMP441 has a MEMS sensor, signal conditioning, an analog-to-digital converter, antialiasing filters, and power management. The output interface is a 24-bit I2S interface 25. The I2S interface 25 is the bus connection between system master 20 and the left microphone 10 and the right microphone 15. The structure of the I2S interface 25 has the serial data SD, the word select WS and the clock SCK as described above in FIG. 1. In this example, the left microphone 10 and the right microphone 15 has a separate channel selection pin 30. The voltage applied to the channel selection pin 30 determines if the microphone places the digitized serial audio in the left channel time slot or the right channel time slot of the serial data SD during transmission. If the microphone is a left microphone 10 the channel selection pin 30 is connected to the ground reference voltage. Alternately, if the microphone is the right microphone 15, the channel selection pin 30 is connected to the power supply voltage source VDD.
The system master 20 may be a digital signal processor (DSP), a microcontroller, or an encoder/decoder (CODEC). The word select signal WS and the system clock SCK is generated by the system master 20 and transferred to the left microphone 10 and the right microphone 15.
FIG. 3 is a block diagram of an example of a stereo speaker system using an I2S input device. The left speaker 60 and the right speaker 65 are driven by an audio amplifier 50 and 55 such as the TFA9882, manufactured by NXP Semiconductors N.V., Eindhoven, the Netherlands. The audio amplifiers 50 and 55 are a monaural, filter-free class-D audio amplifier in a 9-bump WLCSP (Wafer Level Chip-Size Package). It receives audio and control settings via an I2S digital interface 80. A baseband processor 70 has an I2S output circuit 75 that transfers a digitized audio signal on the I2S interface 80 to the audio amplifiers 50 and 55. The serial data SD is connected to the input A1 and the serial clock SCK to the input A2 of the audio amplifiers 50 and 55. The channel select signals WS is connected to the left channel select input WSL at the pin A2 of the audio amplifier 50. The right channel select input WSR at the pin C2 is connected to the battery power supply VBAT. For the audio amplifier 55, the channel select signals WS is connected to the right channel select input WSR at the pin C2 and the left channel select input WSL at the pin A2 is connected to the battery power supply VBAT. The audio amplifiers 50 receives the serial data SD, the serial clock SCK, and the word select signal WS, de-multiplexes the audio data from the left channel and drives the left speaker 60 through a class-D amplifier within the audio amplifiers 50. Similarly, the audio amplifiers 55 receives the serial data SD, the serial clock SCK, and the word select signal WS, de-multiplexes the audio data from the right channel and drives the right speaker 65 through a class-D amplifier within the audio amplifiers 55.
The disadvantage of both examples of FIGS. 2 and 3 is that they require an extra pin on each device strictly for selecting the audio channel. Either a dedicated “UR” pin (in case of the ADMP441), or two word-select pins (in case of the TFA9882). Small size is generally a key requirement for audio devices such as the microphones 10 and 15 of FIG. 2 and the audio amplifiers 50 and 55 of FIG. 3. The extra pins in each example are a major disadvantage that increases size and cost.